The present invention relates to a transfer molded power device, which includes a semiconductor chip that generates heat in operation and a heat sink for cooling the semiconductor chip.
A power device, which includes a semiconductor chip and only one heat sink, which is a copper plate for heat release and also functions as an electrode, is proposed. In the power device, power and ground lines are provided as bonding wires. However, this type of power device has the following problems when the semiconductor chip is downsized for reducing the manufacturing costs. For the downsizing, it becomes necessary to reduce the number of bonding wires, so it becomes impossible to supply a predetermined rated current. Furthermore, although the semiconductor chip operates at a higher speed as the device downsized, the downsizing leads to a larger inductance and increased surge. In addition, the semiconductor chip generates more heat per volume when drawing the predetermined rated current. Therefore, the otherwise lower temperature of the semiconductor chip becomes higher in operation unless the heat is released more efficiently.
In order to address the problem described above, a semiconductor device that includes two heat sinks is proposed. Because heat is released from two sides of the semiconductor chip to the two heat sinks respectively, the later proposed semiconductor device offers improved heat release efficiency compared with the former proposed power device that has only one heat sink. Although the later proposed semiconductor device is molded with a mold resin, the surfaces of the two heat sinks that are opposite from the surfaces facing respectively the semiconductor chip are exposed for improving heat release efficiency.
However, in the later proposed semiconductor device, the semiconductor chip and the heat sinks are relatively very different in thermal expansion coefficient from each other. Therefore, a relatively large stress can be generated in the semiconductor chip under thermal cycling while the later semiconductor device is in operation, and the semiconductor chip is destroyed in the worst case. Specifically, when the later proposed semiconductor device is manufactured, the heat sinks are soldered to the semiconductor chip in a reflow process, in which solders are heated to a predetermined temperature at a heating step to melt the solders and cooled to harden the solders at a subsequent cooling step. To be specific, the semiconductor chip and the heat sinks in the later proposed semiconductor device are substantially made of a single-crystal silicon and copper, respectively. Therefore, due to the difference in thermal expansion coefficient between single-crystal silicon and copper, 3.0 ppm and 17 ppm respectively as shown in FIG. 29, the semiconductor chip and the heat sinks respectively have a compressive stress and a tensile stress directly after the cooling step in the reflow process, as shown in FIG. 30.
When the later proposed semiconductor device is placed at room temperature after the cooling step, the stresses gradually relaxes due to the creeping of the solder connecting the semiconductor chip and the heat sinks. If the stress relaxes sufficiently, a tensile stress is generated in the semiconductor chip due to the difference in thermal expansion coefficient between single-crystal silicon and copper when the semiconductor device is heated again by the heat generated in the semiconductor chip during operation or by the heat from the surrounding environment. While the single crystal silicon that makes up the semiconductor chip remains intact even under more than 600 MPa of compressive stress, the single crystal silicon can be destroyed under a tensile stress of 100 MPa. Therefore, it is the tensile stress that destroys the semiconductor chip in the later semiconductor device.
The semiconductor chip includes p-type base regions and n+-type source regions, which are located in a front surface of an n-type silicon substrate, and a drain electrode, which is located on a back surface of the n-type silicon substrate. The front surface and the back surface face in the opposite direction. In a proposed method for manufacturing the semiconductor chip, a semiconductor wafer of n-type silicon, from which a plurality of the semiconductor chips are made, is thinned in order to reduce the thickness of the semiconductor chip because the ON resistance of the semiconductor chip is lowered by shortening a current path.
Specifically, in a proposed method, the base and source regions, a metallization layer, and a passivation film (SiN film or PIQ film) are formed on a front surface of the wafer, and then the wafer is thinned. Next, a back side electrode layer is formed on a back surface of the wafer. The front surface and the back surface of the wafer face in the opposite direction. In the proposed method, the wafer is thinned entirely before the back side electrode layer is formed, so the wafer is susceptible to warping and becomes fragile in later manufacturing steps.
In the proposed method for manufacturing the semiconductor chip, an n+ region is formed in the back surface of the wafer as an impurity diffusion region for the electric contact between the wafer and the back side electrode layer. Then, the back side electrode layer is formed in contact with the n+ region.
To form the n+ region, either an ion implanting method or a thermal diffusion method is used. The ion implanting method requires an annealing at 500° C. to 700° C. for activating implanted ions close to 100%. In addition, a relatively heavy dose is needed for achieving a relatively high impurity concentration. On the other hand, the thermal diffusion method requires a higher temperature and longer time period than the ion implanting method. However, in both methods, because the n+ region is formed after the metallization layer is formed on the front surface of the wafer, the annealing must be conducted at a temperature lower than the temperature at which the metallization layer softens. For example, when aluminum film is used, the anneal temperature needs to be lower than 450° C. Therefore, in the proposed method, the annealing effect is not sufficient.